1. Field of the Invention
The present invention relates to a Bi-CMOS IC (integrated circuit) device including a self-alignment bipolar transistor capable of very high speed operation and a CMOS transistor provided on a common semiconductor substrate, and a method for producing the same.
2. Description of the Related Art
As mobile communication apparatuses such as cellular telephones have been developed dramatically in recent years, it has been necessary to integrate a high frequency circuit and a highly-integrated logic circuit into a single semiconductor IC. Accordingly, there has been a growing demand for a technique of providing a very high speed self-aligned bipolar transistor (which is suitable for a high speed ECL circuit or a high frequency analog circuit) and a highly-integrated, low power consumption CMOS transistor together on the same semiconductor substrate.
Japanese Laid-open Publication No. 63-281456 discloses a method for producing a Bi-CMOS IC device in which a double-layer polycrystalline silicon self-aligned bipolar transistor (where an emitter lead electrode is self-aligned with a base lead electrode) and a CMOS transistor are provided on the same semiconductor substrate.
Referring to FIGS. 14 to 25, a method for producing a conventional Bi-CMOS IC device will be described. The conventional Bi-CMOS IC device includes NPN bipolar transistor and an N-type MOS transistor integrated on a P-type semiconductor substrate 301.
FIG. 14 illustrates a substrate 20 which includes a P-type silicon semiconductor substrate 301. An N-type buried collector layer 302 is provided on the P-type semiconductor substrate 301. An N-type epitaxial layer (not shown) is provided on the entire surface of the P-type semiconductor substrate 301. An N-type collector layer 303 is provided on the N-type epitaxial layer. A P-type layer 304 of the bipolar transistor for device separation is provided on the N-type epitaxial layer. A P-type well layer 305 of the N-type MOS transistor is provided on the N-type epitaxial layer. The substrate 20 further includes silicon oxide device isolation LOCOS (Local Oxidation of Silicon) films 306a to 306d.
Referring to FIGS. 15 to 19, the substrate 20 illustrated in FIG. 14 is formed as follows.
FIG. 15 illustrates a substrate 20a being subjected to arsenic (As) ion implantation. A resist 350 is first applied on the entire surface of the P-type semiconductor substrate 301 and patterned in a predetermined pattern by a suitable photolithography technique. Then, using the resist 350 as a mask, arsenic ions are implanted into the substrate 20a. The resist 350 is removed after the ion implantation process.
FIG. 16 illustrates a substrate 20b in which the N-type buried collector layer 302 of the NPN bipolar transistor has been formed. The N-type buried collector 302 is formed through a heat treatment at about 1100.degree. C.
Then, an N-type epitaxial layer 351 is grown on the P-type semiconductor substrate 301 illustrated in FIG. 16. A resist is applied on the entire surface of the N-type epitaxial layer 351 and patterned in a predetermined pattern by a photolithography technique. Then, using the resist as a mask, phosphorus (P) ions are implanted into the N-type epitaxial layer 351 so as to form the N-type collector layer 303 (FIG. 18). The resist is removed after the ion implantation process.
FIG. 17 illustrates a substrate 20c being subjected to boron (B) ion implantation, in which the N-type epitaxial layer 351 and another resist 350' have been formed. The resist 350' is applied on the entire surface of the N-type epitaxial layer 351 and patterned in a predetermined pattern by a photolithography technique. Then, using the resist 350' as a mask, boron ions are implanted into the N-type epitaxial layer 351 so as to form the P-type layer 304 and the P-type well layer 305. The resist 350' is removed after the ion implantation process, and a heat treatment at about 1100.degree. C. is performed, thereby forming the N-type collector layer 303 and the P-type layer 304 of the NPN bipolar transistor, and the P-type well layer 305 of the N-type MOS transistor. FIG. 18 illustrates a substrate 20d in which the NPN bipolar transistor has been formed.
Thereafter, a protective oxide film (not shown) and a silicon nitride film (not shown) are grown on the N-type epitaxial layer 351 (the N-type collector layer 303, the P-type layer 304 and P-type well layer 305). Then, a resist is applied on the entire surface of the silicon nitride film patterned in a predetermined pattern by a photolithography technique. Using the resist as a mask, the silicon nitride film is partially etch away and thus patterned. The resist is then removed. Using the patterned silicon nitride film as a mask, the N-type epitaxial layer 351 (the N-type collector layer 303, the P-type layer 304 and P-type well layer 305) is oxidized at about 1000.degree. C. so as to form the device isolation LOCOS films 306a to 306d. After the LOCOS films 306a to 306d are formed, the silicon nitride film and the protective oxide film are removed. FIG. 19 illustrates a substrate 20e in which the device isolation LOCOS films 306a to 306d have been formed.
FIG. 20 illustrates a substrate 30. A gate oxide film 307 is provided on a surface of an N-type epitaxial layer (not shown). A bipolar transistor region 308a is a region where the bipolar transistor is to be formed. An MOS transistor region 308b is a region where the MOS transistor is to be formed. A base lead electrode 309 of the NPN transistor is made of a polycrystalline silicon film. A gate electrode 310 of the N-type MOS transistor is made of a polycrystalline silicon film. An insulation film 311 is provided on the base lead electrode 309. Another insulation film 312 is provided on the gate electrode 310. The substrate 30 also includes an intrinsic base layer 313a of the NPN transistor and an LDD (Lightly Doped Drain) layer 313b of the N-type MOS transistor.
Referring to FIGS. 21 to 25, the substrate 30 illustrated in FIG. 20 is formed as follows.
FIG. 21 illustrates a substrate 30a in which a portion of the gate oxide film 307 corresponding to the bipolar transistor region 308a has been removed. First, the surface of the N-type epitaxial layer 351 (the N-type collector layer 303, the P-type layer 304 and P-type well layer 305) is oxidized at about 900.degree. C., thereby forming the gate oxide film 307 on the entire surface of the N-type epitaxial layer 351. Then, a resist 352 is applied on the entire surface of the gate oxide film 307 and patterned in a predetermined pattern by a photolithography technique so as to have a window (opening) in a region of the resist 352 corresponding to the bipolar transistor region 308a. Using the resist 352 as a mask, a portion of the gate oxide film 307 corresponding to the bipolar transistor region 308a is etched away. The resist 352 is then removed.
FIG. 22 illustrates a substrate 30b in which a polycrystalline silicon film 354 and an insulation film 353 have been formed. First, the polycrystalline silicon film 354 is grown on the entire surface of the substrate 30a from which the resist 352 has been removed. Then, a resist is applied on the polycrystalline silicon film 354 and patterned in a predetermined pattern by a photolithography technique so as to have a window in the bipolar transistor region 308a. Using the resist as a mask, the polycrystalline silicon film 354 is subjected to boron ion implantation, thereby introducing a P-type impurity into the bipolar transistor region 308a. The resist is then removed.
Another resist is applied on the polycrystalline silicon film 354 and patterned in a predetermined pattern by a photolithography technique so as to have a window in the MOS transistor region 308b. Using the resist as a mask, the polycrystalline silicon film 354 is subjected to phosphorus ion implantation, thereby introducing a P-type impurity into the bipolar transistor region 308a. The resist is then removed, and the insulation film 353 is grown on the polycrystalline silicon film 354.
FIG. 23 illustrates a substrate 30c in which the base lead electrode 309, the insulation film 311, the gate electrode 310 and the insulation film 312 have been formed. First, a resist is applied on the insulation film 353 and patterned by a photolithography technique. Then, using the resist as a mask, the insulation film 353 and the polycrystalline silicon film 354 are partially etched away so as to form the base lead electrode 309, the insulation film 311, the gate electrode 310 and the insulation film 312. The resist is then removed.
FIG. 24 illustrates a substrate 30d being subjected to boron ion implantation. First, a resist 355 is applied on the substrate 30d and patterned in a predetermined pattern by a photolithography technique so as to have a window opened in a predetermined region (see FIG. 24). Then, boron ions are implanted into the substrate 30d using the resist 355 and the insulation film 312 as masks so as to form the intrinsic base layer 313a. The resist 355 is removed after the ion implantation process.
FIG. 25 illustrates a substrate 30e being subjected to phosphorus ion implantation. First, a resist 356 is applied on the substrate 30e and patterned in a predetermined pattern by a photolithography technique so as to have a window in a predetermined region (see FIG. 25). Then, phosphorus ions are implanted into the substrate 30e using the resist 356 and the insulation film 311 as masks so as to form the LDD layer 313b. After the LDD layer 313b is formed, the resist 356 is removed.
FIG. 26 illustrates a substrate 30f including a side wall 314a provided on one side surface of each base lead electrode 309 which is closer to an emitter region (a region where an emitter is to be formed), another side wall 314b provided on the other side surface of each base lead electrode 309 which is farther away from the emitter region, another side wall 314c provided on each side surface of the gate electrode 310, and an emitter electrode extraction opening 315 which is defined between the side walls 314a. The substrate 30f is formed as follows.
After the resist 356 is removed from the substrate 30e (FIG. 25), an insulation film is grown on the entire surface of the substrate from which the resist 356 has been removed. Then, an anisotropic etching is performed so as to form the side walls 314a and 314b on the respective side surfaces of each base lead electrode 309, and the side wall 314c on each side surface of the gate electrode 310.
FIG. 27 illustrates a substrate 30g including an emitter electrode 316 of the NPN transistor which is made of a polycrystalline silicon film, a collector electrode 317 of the NPN transistor which is made of the polycrystalline silicon film, an emitter layer 318, a collector contact layer 319, an external base layer 320, and a source-drain layer 321 of the N-type MOS transistor. The substrate 30g illustrated in FIG. 27 is formed as follows.
First, a polycrystalline silicon film is grown on the entire surface of the substrate 30f illustrated in FIG. 26, and is subjected to arsenic ion implantation. A resist is applied on the polycrystalline silicon film and patterned in a predetermined pattern by a photolithography technique. Using the resist as a mask, the polycrystalline silicon film is partially etched away so as to form the emitter electrode 316 and the collector electrode 317. The resist is then removed.
Thereafter, heat treatment at about 900.degree. C. is performed, so that arsenic impurities in the emitter electrode 316 and the collector electrode 317 and boron impurities in the base lead electrode 309 are introduced into the substrate, thereby forming the emitter layer 318, the collector contact layer 319 and the external base layer 320.
Another resist is applied on the surface of the substrate 30g in which the emitter layer 318, the collector contact layer 319 and the external base layer 320 have been formed. The resist is patterned in a predetermined pattern by a photolithography technique. Using the resist, the insulation film 312 and the side walls 314c as masks, the substrate 30g is subjected to arsenic ion implantation so as to form the source-drain layer 321. The resist is removed after the ion implantation process.
Through the above-described process, the base lead electrode 309 and the side walls 314a of the NPN transistor are formed at the same time as the gate electrode 310 and the side walls 314c of the MOS transistor. The emitter electrode extraction opening 315 and the emitter layer 318 are formed in a self-alignment manner with respect to the base lead electrode 309, and the source-drain layer 321 is formed in a self-alignment manner with respect to the gate electrode 310 and the LDD layer 313b. Thus, an LDD structure is obtained in the MOS transistor which improves a hot carrier resistance against hot carriers which may deteriorate the device characteristics. In the bipolar transistor, a base resistance is reduced, as well as a parasitic device component such as a base-collector capacitance or an emitter-base junction capacitance, thereby improving the high frequency characteristics of the device.
The demand for reducing the size of the CMOS IC device while improving the performance thereof is further growing. In fact, a gate oxide film whose thickness is less than 5 nm has been developed.
In the conventional Bi-CMOS IC device and the method for producing the same, a photolithography process is performed after the gate oxide film 307 is formed, so as to remove a portion of the gate oxide film 307 in the bipolar transistor region 308a. Thereafter the polycrystalline silicon film is grown from which the gate electrode 310 is formed. This process in the prior art provides for forming the base electrode 309 of the bipolar transistor and the gate electrode 310 of the MOS transistor from the same polycrystalline silicon film.
During this process, however, a resist is formed directly on the gate oxide film 307. Especially when the thickness of the gate oxide film 307 is as small as about 5 nm or less, the resistance (and thus the reliability) of the gate oxide film 307 may be reduced due to contamination from the resist film or damage from the removal of the resist film. Even when the voltage applied to the gate oxide film 307 is as small as about 3 V, it still can reduce the breakdown voltage and/or increase the amount of leak current over time. As a result, the operating life of such a conventional transistor at about 100.degree. C. is typically only several years.